1 use crate::std::cell::Cell; 2 use crate::std::ops::{Deref, DerefMut}; 3 4 /// Pads and aligns a value to the length of a cache line. 5 #[derive(Clone, Copy, Default, Hash, PartialEq, Eq)] 6 // Starting from Intel's Sandy Bridge, spatial prefetcher is now pulling pairs of 64-byte cache 7 // lines at a time, so we have to align to 128 bytes rather than 64. 8 // 9 // Sources: 10 // - https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf 11 // - https://github.com/facebook/folly/blob/1b5288e6eea6df074758f877c849b6e73bbb9fbb/folly/lang/Align.h#L107 12 // 13 // ARM's big.LITTLE architecture has asymmetric cores and "big" cores have 128-byte cache line size. 14 // 15 // Sources: 16 // - https://www.mono-project.com/news/2016/09/12/arm64-icache/ 17 // 18 // powerpc64 has 128-byte cache line size. 19 // 20 // Sources: 21 // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_ppc64x.go#L9 22 #[cfg_attr( 23 any( 24 target_arch = "x86_64", 25 target_arch = "aarch64", 26 target_arch = "powerpc64", 27 ), 28 repr(align(128)) 29 )] 30 // arm, mips, mips64, and riscv64 have 32-byte cache line size. 31 // 32 // Sources: 33 // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_arm.go#L7 34 // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips.go#L7 35 // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mipsle.go#L7 36 // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips64x.go#L9 37 // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_riscv64.go#L7 38 #[cfg_attr( 39 any( 40 target_arch = "arm", 41 target_arch = "mips", 42 target_arch = "mips32r6", 43 target_arch = "mips64", 44 target_arch = "mips64r6", 45 target_arch = "riscv64", 46 ), 47 repr(align(32)) 48 )] 49 // s390x has 256-byte cache line size. 50 // 51 // Sources: 52 // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_s390x.go#L7 53 #[cfg_attr(target_arch = "s390x", repr(align(256)))] 54 // x86 and wasm have 64-byte cache line size. 55 // 56 // Sources: 57 // - https://github.com/golang/go/blob/dda2991c2ea0c5914714469c4defc2562a907230/src/internal/cpu/cpu_x86.go#L9 58 // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_wasm.go#L7 59 // 60 // All others are assumed to have 64-byte cache line size. 61 #[cfg_attr( 62 not(any( 63 target_arch = "x86_64", 64 target_arch = "aarch64", 65 target_arch = "powerpc64", 66 target_arch = "arm", 67 target_arch = "mips", 68 target_arch = "mips32r6", 69 target_arch = "mips64", 70 target_arch = "mips64r6", 71 target_arch = "riscv64", 72 target_arch = "s390x", 73 )), 74 repr(align(64)) 75 )] 76 pub struct CachePadded<T> { 77 value: T, 78 } 79 80 impl<T> CachePadded<T> { 81 /// Pads and aligns a value to the length of a cache line. new(value: T) -> CachePadded<T>82 pub fn new(value: T) -> CachePadded<T> { 83 CachePadded::<T> { value } 84 } 85 } 86 87 impl<T> Deref for CachePadded<T> { 88 type Target = T; 89 deref(&self) -> &T90 fn deref(&self) -> &T { 91 &self.value 92 } 93 } 94 95 impl<T> DerefMut for CachePadded<T> { deref_mut(&mut self) -> &mut T96 fn deref_mut(&mut self) -> &mut T { 97 &mut self.value 98 } 99 } 100 101 const SPIN_LIMIT: u32 = 6; 102 103 /// Performs quadratic backoff in spin loops. 104 pub struct Backoff { 105 step: Cell<u32>, 106 } 107 108 impl Backoff { 109 /// Creates a new `Backoff`. new() -> Self110 pub fn new() -> Self { 111 Backoff { step: Cell::new(0) } 112 } 113 114 /// Backs off using lightweight spinning. 115 /// 116 /// This method should be used for retrying an operation because another thread made 117 /// progress. i.e. on CAS failure. 118 #[inline] spin_light(&self)119 pub fn spin_light(&self) { 120 let step = self.step.get().min(SPIN_LIMIT); 121 for _ in 0..step.pow(2) { 122 crate::std::hint::spin_loop(); 123 } 124 125 self.step.set(self.step.get() + 1); 126 } 127 128 /// Backs off using heavyweight spinning. 129 /// 130 /// This method should be used in blocking loops where parking the thread is not an option. 131 #[inline] spin_heavy(&self)132 pub fn spin_heavy(&self) { 133 if self.step.get() <= SPIN_LIMIT { 134 for _ in 0..self.step.get().pow(2) { 135 crate::std::hint::spin_loop() 136 } 137 } else { 138 crate::std::thread::yield_now(); 139 } 140 141 self.step.set(self.step.get() + 1); 142 } 143 } 144