1 /*- 2 * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _FENV_H_ 30 #define _FENV_H_ 31 32 #include <sys/types.h> 33 34 #ifndef __fenv_static 35 #define __fenv_static static 36 #endif 37 38 typedef __uint32_t fenv_t; 39 typedef __uint32_t fexcept_t; 40 41 /* Exception flags */ 42 #define FE_INEXACT 0x02000000 43 #define FE_DIVBYZERO 0x04000000 44 #define FE_UNDERFLOW 0x08000000 45 #define FE_OVERFLOW 0x10000000 46 #define FE_INVALID 0x20000000 /* all types of invalid FP ops */ 47 48 /* 49 * The PowerPC architecture has extra invalid flags that indicate the 50 * specific type of invalid operation occurred. These flags may be 51 * tested, set, and cleared---but not masked---separately. All of 52 * these bits are cleared when FE_INVALID is cleared, but only 53 * FE_VXSOFT is set when FE_INVALID is explicitly set in software. 54 */ 55 #define FE_VXCVI 0x00000100 /* invalid integer convert */ 56 #define FE_VXSQRT 0x00000200 /* square root of a negative */ 57 #define FE_VXSOFT 0x00000400 /* software-requested exception */ 58 #define FE_VXVC 0x00080000 /* ordered comparison involving NaN */ 59 #define FE_VXIMZ 0x00100000 /* inf * 0 */ 60 #define FE_VXZDZ 0x00200000 /* 0 / 0 */ 61 #define FE_VXIDI 0x00400000 /* inf / inf */ 62 #define FE_VXISI 0x00800000 /* inf - inf */ 63 #define FE_VXSNAN 0x01000000 /* operation on a signalling NaN */ 64 #define FE_ALL_INVALID (FE_VXCVI | FE_VXSQRT | FE_VXSOFT | FE_VXVC | \ 65 FE_VXIMZ | FE_VXZDZ | FE_VXIDI | FE_VXISI | \ 66 FE_VXSNAN | FE_INVALID) 67 #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ 68 FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW) 69 70 /* Rounding modes */ 71 #define FE_TONEAREST 0x0000 72 #define FE_TOWARDZERO 0x0001 73 #define FE_UPWARD 0x0002 74 #define FE_DOWNWARD 0x0003 75 #define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \ 76 FE_UPWARD | FE_TOWARDZERO) 77 78 __BEGIN_DECLS 79 80 /* Default floating-point environment */ 81 extern const fenv_t __fe_dfl_env; 82 #define FE_DFL_ENV (&__fe_dfl_env) 83 84 /* We need to be able to map status flag positions to mask flag positions */ 85 #define _FPUSW_SHIFT 22 86 #define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \ 87 FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT) 88 89 #ifndef _SOFT_FLOAT 90 #define __mffs(__env) __asm __volatile("mffs %0" : "=f" (*(__env))) 91 #define __mtfsf(__env) __asm __volatile("mtfsf 255,%0" : : "f" (__env)) 92 #else 93 #define __mffs(__env) 94 #define __mtfsf(__env) 95 #endif 96 97 union __fpscr { 98 double __d; 99 struct { 100 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ 101 fenv_t __reg; 102 __uint32_t __junk; 103 #else 104 __uint32_t __junk; 105 fenv_t __reg; 106 #endif 107 } __bits; 108 }; 109 110 __fenv_static inline int 111 feclearexcept(int __excepts) 112 { 113 union __fpscr __r; 114 115 if (__excepts & FE_INVALID) 116 __excepts |= FE_ALL_INVALID; 117 __mffs(&__r.__d); 118 __r.__bits.__reg &= ~__excepts; 119 __mtfsf(__r.__d); 120 return (0); 121 } 122 123 __fenv_static inline int 124 fegetexceptflag(fexcept_t *__flagp, int __excepts) 125 { 126 union __fpscr __r; 127 128 __mffs(&__r.__d); 129 *__flagp = __r.__bits.__reg & __excepts; 130 return (0); 131 } 132 133 __fenv_static inline int 134 fesetexceptflag(const fexcept_t *__flagp, int __excepts) 135 { 136 union __fpscr __r; 137 138 if (__excepts & FE_INVALID) 139 __excepts |= FE_ALL_EXCEPT; 140 __mffs(&__r.__d); 141 __r.__bits.__reg &= ~__excepts; 142 __r.__bits.__reg |= *__flagp & __excepts; 143 __mtfsf(__r.__d); 144 return (0); 145 } 146 147 __fenv_static inline int 148 feraiseexcept(int __excepts) 149 { 150 union __fpscr __r; 151 152 if (__excepts & FE_INVALID) 153 __excepts |= FE_VXSOFT; 154 __mffs(&__r.__d); 155 __r.__bits.__reg |= __excepts; 156 __mtfsf(__r.__d); 157 return (0); 158 } 159 160 __fenv_static inline int 161 fetestexcept(int __excepts) 162 { 163 union __fpscr __r; 164 165 __mffs(&__r.__d); 166 return (__r.__bits.__reg & __excepts); 167 } 168 169 __fenv_static inline int 170 fegetround(void) 171 { 172 union __fpscr __r; 173 174 __mffs(&__r.__d); 175 return (__r.__bits.__reg & _ROUND_MASK); 176 } 177 178 __fenv_static inline int 179 fesetround(int __round) 180 { 181 union __fpscr __r; 182 183 if (__round & ~_ROUND_MASK) 184 return (-1); 185 __mffs(&__r.__d); 186 __r.__bits.__reg &= ~_ROUND_MASK; 187 __r.__bits.__reg |= __round; 188 __mtfsf(__r.__d); 189 return (0); 190 } 191 192 __fenv_static inline int 193 fegetenv(fenv_t *__envp) 194 { 195 union __fpscr __r; 196 197 __mffs(&__r.__d); 198 *__envp = __r.__bits.__reg; 199 return (0); 200 } 201 202 __fenv_static inline int 203 feholdexcept(fenv_t *__envp) 204 { 205 union __fpscr __r; 206 207 __mffs(&__r.__d); 208 *__envp = __r.__d; 209 __r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK); 210 __mtfsf(__r.__d); 211 return (0); 212 } 213 214 __fenv_static inline int 215 fesetenv(const fenv_t *__envp) 216 { 217 union __fpscr __r; 218 219 __r.__bits.__reg = *__envp; 220 __mtfsf(__r.__d); 221 return (0); 222 } 223 224 __fenv_static inline int 225 feupdateenv(const fenv_t *__envp) 226 { 227 union __fpscr __r; 228 229 __mffs(&__r.__d); 230 __r.__bits.__reg &= FE_ALL_EXCEPT; 231 __r.__bits.__reg |= *__envp; 232 __mtfsf(__r.__d); 233 return (0); 234 } 235 236 #if __BSD_VISIBLE 237 238 /* We currently provide no external definitions of the functions below. */ 239 240 static inline int 241 feenableexcept(int __mask) 242 { 243 union __fpscr __r; 244 fenv_t __oldmask; 245 246 __mffs(&__r.__d); 247 __oldmask = __r.__bits.__reg; 248 __r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT; 249 __mtfsf(__r.__d); 250 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); 251 } 252 253 static inline int 254 fedisableexcept(int __mask) 255 { 256 union __fpscr __r; 257 fenv_t __oldmask; 258 259 __mffs(&__r.__d); 260 __oldmask = __r.__bits.__reg; 261 __r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT); 262 __mtfsf(__r.__d); 263 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT); 264 } 265 266 static inline int 267 fegetexcept(void) 268 { 269 union __fpscr __r; 270 271 __mffs(&__r.__d); 272 return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT); 273 } 274 275 #endif /* __BSD_VISIBLE */ 276 277 __END_DECLS 278 279 #endif /* !_FENV_H_ */ 280